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<div class="title">xdualsplitter_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gad75ea00710a7538df61fcdf5a8a8e3cb"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gad75ea00710a7538df61fcdf5a8a8e3cb">XDUALSPLITTER_HW_H_</a></td></tr>
<tr class="memdesc:gad75ea00710a7538df61fcdf5a8a8e3cb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__dual__splitter__v1__0.html#gad75ea00710a7538df61fcdf5a8a8e3cb">More...</a><br /></td></tr>
<tr class="separator:gad75ea00710a7538df61fcdf5a8a8e3cb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core registers offsets</div></td></tr>
<tr class="memitem:ga9aa22487fb466a14cd0ba59a0cb68839"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga9aa22487fb466a14cd0ba59a0cb68839">XDUSP_GENR_CTL_OFFSET</a>&#160;&#160;&#160;0x0000</td></tr>
<tr class="memdesc:ga9aa22487fb466a14cd0ba59a0cb68839"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Control register offset.  <a href="group__dual__splitter__v1__0.html#ga9aa22487fb466a14cd0ba59a0cb68839">More...</a><br /></td></tr>
<tr class="separator:ga9aa22487fb466a14cd0ba59a0cb68839"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae0d2add2d78533708bab0984ddb23131"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gae0d2add2d78533708bab0984ddb23131">XDUSP_GENR_ERR_OFFSET</a>&#160;&#160;&#160;0x0008</td></tr>
<tr class="memdesc:gae0d2add2d78533708bab0984ddb23131"><td class="mdescLeft">&#160;</td><td class="mdescRight">General Error register offset.  <a href="group__dual__splitter__v1__0.html#gae0d2add2d78533708bab0984ddb23131">More...</a><br /></td></tr>
<tr class="separator:gae0d2add2d78533708bab0984ddb23131"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9a56efd4e26a05c36598f24949094dda"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga9a56efd4e26a05c36598f24949094dda">XDUSP_IRQ_EN_OFFSET</a>&#160;&#160;&#160;0x000C</td></tr>
<tr class="memdesc:ga9a56efd4e26a05c36598f24949094dda"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ Enable register offset.  <a href="group__dual__splitter__v1__0.html#ga9a56efd4e26a05c36598f24949094dda">More...</a><br /></td></tr>
<tr class="separator:ga9a56efd4e26a05c36598f24949094dda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad649caaa67afb83491e3f52f4ae9f86d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gad649caaa67afb83491e3f52f4ae9f86d">XDUSP_TIME_CTL_OFFSET</a>&#160;&#160;&#160;0x0020</td></tr>
<tr class="memdesc:gad649caaa67afb83491e3f52f4ae9f86d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time Control register offset.  <a href="group__dual__splitter__v1__0.html#gad649caaa67afb83491e3f52f4ae9f86d">More...</a><br /></td></tr>
<tr class="separator:gad649caaa67afb83491e3f52f4ae9f86d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3853f0c033aa888b7d81c83d2f5f9599"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga3853f0c033aa888b7d81c83d2f5f9599">XDUSP_CORE_CTL_OFFSET</a>&#160;&#160;&#160;0x0100</td></tr>
<tr class="memdesc:ga3853f0c033aa888b7d81c83d2f5f9599"><td class="mdescLeft">&#160;</td><td class="mdescRight">Core Control register offset.  <a href="group__dual__splitter__v1__0.html#ga3853f0c033aa888b7d81c83d2f5f9599">More...</a><br /></td></tr>
<tr class="separator:ga3853f0c033aa888b7d81c83d2f5f9599"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">General control register bit masks</div></td></tr>
<tr class="memitem:ga409aff15607ec53867669d1a1bc04f13"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga409aff15607ec53867669d1a1bc04f13">XDUSP_GENR_CTL_EN_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga409aff15607ec53867669d1a1bc04f13"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable mask.  <a href="group__dual__splitter__v1__0.html#ga409aff15607ec53867669d1a1bc04f13">More...</a><br /></td></tr>
<tr class="separator:ga409aff15607ec53867669d1a1bc04f13"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8c493f7fecb3dcc8cfd270eac6fd68b5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga8c493f7fecb3dcc8cfd270eac6fd68b5">XDUSP_GENR_CTL_RUE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga8c493f7fecb3dcc8cfd270eac6fd68b5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register update enable mask.  <a href="group__dual__splitter__v1__0.html#ga8c493f7fecb3dcc8cfd270eac6fd68b5">More...</a><br /></td></tr>
<tr class="separator:ga8c493f7fecb3dcc8cfd270eac6fd68b5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3643ee94cd6200a619faed8ca73a5b3f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga3643ee94cd6200a619faed8ca73a5b3f">XDUSP_GENR_CTL_RST_MASK</a>&#160;&#160;&#160;0x80000000</td></tr>
<tr class="memdesc:ga3643ee94cd6200a619faed8ca73a5b3f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset mask.  <a href="group__dual__splitter__v1__0.html#ga3643ee94cd6200a619faed8ca73a5b3f">More...</a><br /></td></tr>
<tr class="separator:ga3643ee94cd6200a619faed8ca73a5b3f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Error register bit masks</div></td></tr>
<tr class="memitem:ga5bc1b1b7233576abbb54e8880d10c21b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga5bc1b1b7233576abbb54e8880d10c21b">XDUSP_ERR_EOL_EARLY_MASK</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga5bc1b1b7233576abbb54e8880d10c21b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: End of line early mask.  <a href="group__dual__splitter__v1__0.html#ga5bc1b1b7233576abbb54e8880d10c21b">More...</a><br /></td></tr>
<tr class="separator:ga5bc1b1b7233576abbb54e8880d10c21b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa3083e69b468e8b018f3af6d495d1c9a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gaa3083e69b468e8b018f3af6d495d1c9a">XDUSP_ERR_EOL_LATE_MASK</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaa3083e69b468e8b018f3af6d495d1c9a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: End of line late mask.  <a href="group__dual__splitter__v1__0.html#gaa3083e69b468e8b018f3af6d495d1c9a">More...</a><br /></td></tr>
<tr class="separator:gaa3083e69b468e8b018f3af6d495d1c9a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5c3df0fa33c98e366e3721e5e41e005"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gad5c3df0fa33c98e366e3721e5e41e005">XDUSP_ERR_SOF_EARLY_MASK</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gad5c3df0fa33c98e366e3721e5e41e005"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: Start of frame early mask.  <a href="group__dual__splitter__v1__0.html#gad5c3df0fa33c98e366e3721e5e41e005">More...</a><br /></td></tr>
<tr class="separator:gad5c3df0fa33c98e366e3721e5e41e005"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaa0cbd7bfe18600c16d01397267ca09a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gaaa0cbd7bfe18600c16d01397267ca09a">XDUSP_ERR_SOF_LATE_MASK</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gaaa0cbd7bfe18600c16d01397267ca09a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Error: Start of frame late mask.  <a href="group__dual__splitter__v1__0.html#gaaa0cbd7bfe18600c16d01397267ca09a">More...</a><br /></td></tr>
<tr class="separator:gaaa0cbd7bfe18600c16d01397267ca09a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9702539641dd20a1668e5ca074de7f25"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga9702539641dd20a1668e5ca074de7f25">XDUSP_ALL_ERR_MASK</a></td></tr>
<tr class="memdesc:ga9702539641dd20a1668e5ca074de7f25"><td class="mdescLeft">&#160;</td><td class="mdescRight">All error mask.  <a href="group__dual__splitter__v1__0.html#ga9702539641dd20a1668e5ca074de7f25">More...</a><br /></td></tr>
<tr class="separator:ga9702539641dd20a1668e5ca074de7f25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Time control register bit masks and shifts</div></td></tr>
<tr class="memitem:ga54161faf9be861f7f7a13aef50eb000b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga54161faf9be861f7f7a13aef50eb000b">XDUSP_TIME_CTL_WIDTH_MASK</a>&#160;&#160;&#160;0x0000FFFF</td></tr>
<tr class="memdesc:ga54161faf9be861f7f7a13aef50eb000b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Image width mask.  <a href="group__dual__splitter__v1__0.html#ga54161faf9be861f7f7a13aef50eb000b">More...</a><br /></td></tr>
<tr class="separator:ga54161faf9be861f7f7a13aef50eb000b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37b7b7c851b06e75cc1f5ae389a0e8de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga37b7b7c851b06e75cc1f5ae389a0e8de">XDUSP_TIME_CTL_HEIGHT_MASK</a>&#160;&#160;&#160;0xFFFF0000</td></tr>
<tr class="memdesc:ga37b7b7c851b06e75cc1f5ae389a0e8de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Image height mask.  <a href="group__dual__splitter__v1__0.html#ga37b7b7c851b06e75cc1f5ae389a0e8de">More...</a><br /></td></tr>
<tr class="separator:ga37b7b7c851b06e75cc1f5ae389a0e8de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga064f0f56cff150e7c031d151a1ceadbd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga064f0f56cff150e7c031d151a1ceadbd">XDUSP_TIME_CTL_HEIGHT_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga064f0f56cff150e7c031d151a1ceadbd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Image height shift.  <a href="group__dual__splitter__v1__0.html#ga064f0f56cff150e7c031d151a1ceadbd">More...</a><br /></td></tr>
<tr class="separator:ga064f0f56cff150e7c031d151a1ceadbd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Core control register masks and shifts</div></td></tr>
<tr class="memitem:ga2cff3acfb111c7e366565f719680edd3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga2cff3acfb111c7e366565f719680edd3">XDUSP_CORE_CTL_IN_SAMPLES_MASK</a>&#160;&#160;&#160;0x000000FF</td></tr>
<tr class="memdesc:ga2cff3acfb111c7e366565f719680edd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input samples mask.  <a href="group__dual__splitter__v1__0.html#ga2cff3acfb111c7e366565f719680edd3">More...</a><br /></td></tr>
<tr class="separator:ga2cff3acfb111c7e366565f719680edd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad365e0bf9914979373862e2b0247ab9e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gad365e0bf9914979373862e2b0247ab9e">XDUSP_CORE_CTL_OUT_SAMPLES_MASK</a>&#160;&#160;&#160;0x0000FF00</td></tr>
<tr class="memdesc:gad365e0bf9914979373862e2b0247ab9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output samples mask.  <a href="group__dual__splitter__v1__0.html#gad365e0bf9914979373862e2b0247ab9e">More...</a><br /></td></tr>
<tr class="separator:gad365e0bf9914979373862e2b0247ab9e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf78ad6b596b92871ae752278c0b2f68f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gaf78ad6b596b92871ae752278c0b2f68f">XDUSP_CORE_CTL_IMG_SEG_MASK</a>&#160;&#160;&#160;0x00FF0000</td></tr>
<tr class="memdesc:gaf78ad6b596b92871ae752278c0b2f68f"><td class="mdescLeft">&#160;</td><td class="mdescRight">No of image segments mask.  <a href="group__dual__splitter__v1__0.html#gaf78ad6b596b92871ae752278c0b2f68f">More...</a><br /></td></tr>
<tr class="separator:gaf78ad6b596b92871ae752278c0b2f68f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22ef43326e4ba226883fa319353cf978"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga22ef43326e4ba226883fa319353cf978">XDUSP_CORE_CTL_OVRLAP_SEG_MASK</a>&#160;&#160;&#160;0xFF000000</td></tr>
<tr class="memdesc:ga22ef43326e4ba226883fa319353cf978"><td class="mdescLeft">&#160;</td><td class="mdescRight">No of over- lapping segments mask.  <a href="group__dual__splitter__v1__0.html#ga22ef43326e4ba226883fa319353cf978">More...</a><br /></td></tr>
<tr class="separator:ga22ef43326e4ba226883fa319353cf978"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabc53d9a930e928bda2434053abf9214e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gabc53d9a930e928bda2434053abf9214e">XDUSP_CORE_CTL_OUT_SAMPLES_SHIFT</a>&#160;&#160;&#160;8</td></tr>
<tr class="memdesc:gabc53d9a930e928bda2434053abf9214e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output samples shift.  <a href="group__dual__splitter__v1__0.html#gabc53d9a930e928bda2434053abf9214e">More...</a><br /></td></tr>
<tr class="separator:gabc53d9a930e928bda2434053abf9214e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f6afd079b92c498a29e2aff60dfee6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga2f6afd079b92c498a29e2aff60dfee6f">XDUSP_CORE_CTL_IMG_SEG_SHIFT</a>&#160;&#160;&#160;16</td></tr>
<tr class="memdesc:ga2f6afd079b92c498a29e2aff60dfee6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">No of image segments shift.  <a href="group__dual__splitter__v1__0.html#ga2f6afd079b92c498a29e2aff60dfee6f">More...</a><br /></td></tr>
<tr class="separator:ga2f6afd079b92c498a29e2aff60dfee6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac37e45ef0d15293e4144c6317e66ce4d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gac37e45ef0d15293e4144c6317e66ce4d">XDUSP_CORE_CTL_OVRLAP_SEG_SHIFT</a>&#160;&#160;&#160;24</td></tr>
<tr class="memdesc:gac37e45ef0d15293e4144c6317e66ce4d"><td class="mdescLeft">&#160;</td><td class="mdescRight">No of overlapping segments shift.  <a href="group__dual__splitter__v1__0.html#gac37e45ef0d15293e4144c6317e66ce4d">More...</a><br /></td></tr>
<tr class="separator:gac37e45ef0d15293e4144c6317e66ce4d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Device register I/O APIs</div></td></tr>
<tr class="memitem:ga837e3f05114107c687608ee56e01bfad"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga837e3f05114107c687608ee56e01bfad">XDualSplitter_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:ga837e3f05114107c687608ee56e01bfad"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input operation.  <a href="group__dual__splitter__v1__0.html#ga837e3f05114107c687608ee56e01bfad">More...</a><br /></td></tr>
<tr class="separator:ga837e3f05114107c687608ee56e01bfad"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d7f7a7af0fd9de6643900e9371dccdd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga7d7f7a7af0fd9de6643900e9371dccdd">XDualSplitter_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:ga7d7f7a7af0fd9de6643900e9371dccdd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output operation.  <a href="group__dual__splitter__v1__0.html#ga7d7f7a7af0fd9de6643900e9371dccdd">More...</a><br /></td></tr>
<tr class="separator:ga7d7f7a7af0fd9de6643900e9371dccdd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga44eddc0730f101cf5dbe56e4c1095a57"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#ga44eddc0730f101cf5dbe56e4c1095a57">XDualSplitter_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__dual__splitter__v1__0.html#ga837e3f05114107c687608ee56e01bfad">XDualSplitter_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:ga44eddc0730f101cf5dbe56e4c1095a57"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads a value from a Dual Splitter core's register.  <a href="group__dual__splitter__v1__0.html#ga44eddc0730f101cf5dbe56e4c1095a57">More...</a><br /></td></tr>
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<tr class="memitem:gaf9746d088835a772833e7d5482adcdfd"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__dual__splitter__v1__0.html#gaf9746d088835a772833e7d5482adcdfd">XDualSplitter_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__dual__splitter__v1__0.html#ga7d7f7a7af0fd9de6643900e9371dccdd">XDualSplitter_Out32</a>((BaseAddress) + (u32)(RegOffset), (Data))</td></tr>
<tr class="memdesc:gaf9746d088835a772833e7d5482adcdfd"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes a value into a Dual Splitter core's register.  <a href="group__dual__splitter__v1__0.html#gaf9746d088835a772833e7d5482adcdfd">More...</a><br /></td></tr>
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